1. Field of the Invention
The invention relates in general to a frequency synthesizer of a phase locked loop, and in particular, to a multi-band frequency synthesizer of a phase locked loop capable of synthesizing multi-frequency in multi-bands.
2. Description of the Related Art
A phase locked loop (PLL) is an electronic control system, locking in the phase of a reference signal. FIG. 1 is a block diagram of conventional PLL 100. PLL 100 comprises phase detector 110, loop filter 120, and voltage controlled oscillator (VCO) 130. Phase detector 110 is typically a mixer, comparing reference signal Sref and output signal Svco from voltage controlled oscillator 130 in terms of both their frequency and phase difference, and outputting a difference signal to loop filter 120. Loop filter 120 drives voltage controlled oscillator 130 according to the difference signal, so that the phase difference between output signal Svco of voltage controlled oscillator 130 and reference signal Sref remains at a constant level, i.e., output signal Svco locks to reference signal Sref at an identical frequency.
Phase locked loops are being applied in a variety of telecommunication and electronic applications, e.g., frequency synthesis, carrier or timing recovery, and frequency modulation/demodulation. FIG. 2 is a block diagram of a conventional. PLL frequency synthesizer 200. PLL frequency synthesizer 200 comprises phase detector 210, loop filter 220, voltage controlled oscillator 230, and frequency divider 240. The difference between PLL frequency synthesizer 200 and 100 lies in that output signal Svco of voltage controlled oscillator 230 is transmitted to frequency divider 240, and not transmitted to phase detector 210 instead. Frequency divider 240 divides the frequency of output signal Svco of voltage controlled oscillator 230 by N, and then outputs frequency divided signal Sdiv to phase detector 210 for a comparison with the reference signal. When frequency divided signal Sdiv locks to reference signal Sref both signals have an identical frequency, and the frequency of output signal Svco is N times that of reference signal Sref. Thus we can change the frequency division divisor of frequency divider 240 to generate a plurality of output signal Svco with stable frequencies.
Telecommunication and electronic apparatuses are being required to comply with more specifications and regulations as technology advances, for example, a handheld apparatus compliant with both IEEE 802.11b/g and 802.11a, or a handset compliant with Cellular Band (900 MHz) and PCS Band (1900 MHz) specifications. Typically, the differences between frequency bands used by the telecommunication specifications are large, such that a single voltage controlled oscillator cannot cover spectrum requirements of the all PLL frequency synthesizers for various telecommunication specifications. Thus, an electronic telecommunication apparatus is required to include PLL frequency synthesizers for different operation bands to support various telecommunication standards, to comply with telecommunication specification requirements at different bands. Consequently, system complexity and manufacturing costs are increased.
It is desirable to share some components in the PLL frequency synthesizer, while forming a multi-band of PLL synthesizer, to drastically decrease system complexity and cost of electronic telecommunication apparatuses supporting various telecommunication standards.
Thus a need exists for a PLL frequency synthesizer in an electronic telecommunication apparatus compliant with multiple telecommunication specifications, capable of sharing a specific component and switching mechanism, and reducing system complexity and cost, while meeting specific design specifications.